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10 merged results for "Advancements in Semiconductor Devices and Circuit Design"

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  1. DESIGN OF LOW POWER CARRY SKIP ADDER USING DTCMOS

    Kumar, T.R.Dinesh, Sundaram, K.Mohana, Bennet, M.Anto, .R, Aruna · 2017 · International Journal on Smart Sensing and Intelligent Systems

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.21307/ijssis-2017-252

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  2. DEVICE CHARACTERISATION OF SHORT CHANNEL DEVICES AND ITS IMPACT ON CMOS CIRCUIT DESIGN

    Kiran Agarwa, Dinesh K Anvekar, Venkateswarlu V · 2012

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5121/vlsic.2012.3514

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  3. Design and Implementation of Low Power Logic Gates For IOT Devices

    Bhavik Bafna, K. B. Ramesh · 2024 · Journal of Optoelectronics and Communication

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.12671452

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  4. 3D Integrated Circuit (3D IC) Technology and Its Applications

    Zhao, Gang, Song, Cen, Wu, Binghan · 2024 · Journal of Industrial Engineering and Applied Science

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.12794429

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  5. Optimization of Semiconductor Chip Design Using Artificial Intelligence

    Song, Cen, Wu, Binghan, Zhao, Gang · 2024 · Journal of Industrial Engineering and Applied Science

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.12798359

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  6. Machine Learning for Next-Generation Power, Performance, and Area Optimization in Semiconductor Design

    Rashmitha Reddy Vuppunuthula · 2021 · European Journal of Advances in Engineering and Technology

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.14506268

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    • not scoredRetraction Watch retraction: No retraction notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete. Source: Retraction Watch; license: CC BY 4.0
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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  7. ELECTRONIC DEVICES AND CIRCUITS

    S. N. SIVARAJ, M. VIJAYAKARTHICK, S. SATHISHBABU · 2025

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.15533865

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  8. A New N-Fold Flip-Flop with Output Enable

    Ben Zid, Dr. Mounir Al Jilani · 2013 · International Journal of Embedded Systems and Applications (IJESA)

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.17962588

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  9. STRATEGIES FOR REDUCING POWER CONSUMPTION DURING IC TESTING: POWER-AWARE DFT IN PRACTICE

    Sheetal Kaul · 2026 · IPHO-Journal of Advance Research in Science And Engineering

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.19354854

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

  10. A New N-Fold Flip-Flop with Output Enable

    Mounir Zid, Carlo Pistritto, Rached Tourki, Alberto Scandurra · 2013

    limited evidence Transparent signal score 43/100 · policy 1.0.0

    Found in zenodo · DOI 10.5281/zenodo.3466976

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    • cautionMetadata completeness: 5 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer