Disturbance‐Aware On‐Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator

Jaehyeon Kang, Jongun Won, Narae Han, Sangjun Hong, Jee‐Eun Yang, Sangwook Kim, Sangbum Kim

Open source

DOI: 10.1002/advs.202417635
Published: 2025-05-20
Container: Advanced Science
Publisher: Wiley
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1002/advs.202417635,
  title = {Disturbance‐Aware On‐Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator},
  author = {Jaehyeon Kang and Jongun Won and Narae Han and Sangjun Hong and Jee‐Eun Yang and Sangwook Kim and Sangbum Kim},
  year = {2025},
  journal = {Advanced Science},
  doi = {10.1002/advs.202417635},
  url = {https://doi.org/10.1002/advs.202417635}
}

RIS

TY  - JOUR
TI  - Disturbance‐Aware On‐Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator
AU  - Jaehyeon Kang
AU  - Jongun Won
AU  - Narae Han
AU  - Sangjun Hong
AU  - Jee‐Eun Yang
AU  - Sangwook Kim
AU  - Sangbum Kim
PY  - 2025
JO  - Advanced Science
DO  - 10.1002/advs.202417635
UR  - https://doi.org/10.1002/advs.202417635
ER  -

APA

Kang, J., Won, J., Han, N., Hong, S., Yang, J., Kim, S., & Kim, S. (2025). Disturbance‐Aware On‐Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator. Advanced Science. https://doi.org/10.1002/advs.202417635

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crossref · retrieved 2026-11-10T06:23:06.502Z