Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA
- DOI
- 10.1007/978-3-031-87995-1_4
- Published
- 2025
- Container
- Lecture Notes in Computer Science
- Publisher
- Springer Nature Switzerland
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1007/978-3-031-87995-1_4,
title = {Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA},
author = {Hiroshi Nakano and Krzysztof Blachut and Kamil Jeziorek and Piotr Wzorek and Manon Dampfhoffer and Thomas Mesquida and Hiroaki Nishi and Tomasz Kryjak and Thomas Dalgaty},
year = {2025},
journal = {Lecture Notes in Computer Science},
doi = {10.1007/978-3-031-87995-1_4},
url = {https://doi.org/10.1007/978-3-031-87995-1_4}
}RIS
TY - JOUR TI - Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA AU - Hiroshi Nakano AU - Krzysztof Blachut AU - Kamil Jeziorek AU - Piotr Wzorek AU - Manon Dampfhoffer AU - Thomas Mesquida AU - Hiroaki Nishi AU - Tomasz Kryjak AU - Thomas Dalgaty PY - 2025 JO - Lecture Notes in Computer Science DO - 10.1007/978-3-031-87995-1_4 UR - https://doi.org/10.1007/978-3-031-87995-1_4 ER -
APA
Nakano, H., Blachut, K., Jeziorek, K., Wzorek, P., Dampfhoffer, M., Mesquida, T., Nishi, H., Kryjak, T., & Dalgaty, T. (2025). Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA. Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-031-87995-1_4
Source records
- crossref · retrieved 2026-09-25T08:12:09.741Z