Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs
- DOI
- 10.1007/978-3-319-25279-7_2
- Published
- 2015
- Container
- IFIP Advances in Information and Communication Technology
- Publisher
- Springer International Publishing
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1007/978-3-319-25279-7_2,
title = {Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs},
author = {Sreenivaas S. Muthyala and Nur A. Touba},
year = {2015},
journal = {IFIP Advances in Information and Communication Technology},
doi = {10.1007/978-3-319-25279-7_2},
url = {https://doi.org/10.1007/978-3-319-25279-7_2}
}RIS
TY - JOUR TI - Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs AU - Sreenivaas S. Muthyala AU - Nur A. Touba PY - 2015 JO - IFIP Advances in Information and Communication Technology DO - 10.1007/978-3-319-25279-7_2 UR - https://doi.org/10.1007/978-3-319-25279-7_2 ER -
APA
Muthyala, S. S., & Touba, N. A. (2015). Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs. IFIP Advances in Information and Communication Technology. https://doi.org/10.1007/978-3-319-25279-7_2
Source records
- crossref · retrieved 2026-09-25T07:02:38.028Z