8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology
- DOI
- 10.1007/978-3-319-25279-7_6
- Published
- 2015
- Container
- IFIP Advances in Information and Communication Technology
- Publisher
- Springer International Publishing
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1007/978-3-319-25279-7_6,
title = {8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology},
author = {Farshad Moradi and Mohammad Tohidi and Behzad Zeinali and Jens K. Madsen},
year = {2015},
journal = {IFIP Advances in Information and Communication Technology},
doi = {10.1007/978-3-319-25279-7_6},
url = {https://doi.org/10.1007/978-3-319-25279-7_6}
}RIS
TY - JOUR TI - 8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology AU - Farshad Moradi AU - Mohammad Tohidi AU - Behzad Zeinali AU - Jens K. Madsen PY - 2015 JO - IFIP Advances in Information and Communication Technology DO - 10.1007/978-3-319-25279-7_6 UR - https://doi.org/10.1007/978-3-319-25279-7_6 ER -
APA
Moradi, F., Tohidi, M., Zeinali, B., & Madsen, J. K. (2015). 8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology. IFIP Advances in Information and Communication Technology. https://doi.org/10.1007/978-3-319-25279-7_6
Source records
- crossref · retrieved 2026-09-25T20:57:23.945Z