VHDL als Entwurfs- und Simulationssprache
- DOI
- 10.1007/978-3-540-73673-8_4
- Published
- Not recorded
- Container
- Springer-Lehrbuch
- Publisher
- Springer Berlin Heidelberg
- Open access
- unknown
Credibility signals
uncertain Score 58/100 under policy 1.0.0. This is a metadata assessment, not a judgment of the paper's conclusions.
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- cautionMetadata completeness: 4 of 6 scored descriptive metadata groups are present; missing fields increase uncertainty.
Cite this work
BibTeX
@article{allodium:10.1007/978-3-540-73673-8_4,
title = {VHDL als Entwurfs- und Simulationssprache},
journal = {Springer-Lehrbuch},
doi = {10.1007/978-3-540-73673-8_4},
url = {https://doi.org/10.1007/978-3-540-73673-8_4}
}RIS
TY - JOUR TI - VHDL als Entwurfs- und Simulationssprache JO - Springer-Lehrbuch DO - 10.1007/978-3-540-73673-8_4 UR - https://doi.org/10.1007/978-3-540-73673-8_4 ER -
APA
VHDL als Entwurfs- und Simulationssprache. (n.d.). Springer-Lehrbuch. https://doi.org/10.1007/978-3-540-73673-8_4
Source records
- crossref · retrieved 2026-09-25T15:11:49.761Z