Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip

Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu

Open source

DOI
10.1007/978-3-642-24403-2_19
Published
2011
Container
Lecture Notes in Computer Science
Publisher
Springer Berlin Heidelberg
Open access
unknown

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BibTeX

@article{allodium:10.1007/978-3-642-24403-2_19,
  title = {Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip},
  author = {Xiaohang Wang and Maurizio Palesi and Mei Yang and Yingtao Jiang and Michael C. Huang and Peng Liu},
  year = {2011},
  journal = {Lecture Notes in Computer Science},
  doi = {10.1007/978-3-642-24403-2_19},
  url = {https://doi.org/10.1007/978-3-642-24403-2_19}
}

RIS

TY  - JOUR
TI  - Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip
AU  - Xiaohang Wang
AU  - Maurizio Palesi
AU  - Mei Yang
AU  - Yingtao Jiang
AU  - Michael C. Huang
AU  - Peng Liu
PY  - 2011
JO  - Lecture Notes in Computer Science
DO  - 10.1007/978-3-642-24403-2_19
UR  - https://doi.org/10.1007/978-3-642-24403-2_19
ER  - 

APA

Wang, X., Palesi, M., Yang, M., Jiang, Y., Huang, M. C., & Liu, P. (2011). Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-642-24403-2_19

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