System-level FPGA validation of a trainable and robust multiplier-free spiking neural network
- DOI
- 10.1016/j.isci.2026.115985
- Published
- 2026-06
- Container
- iScience
- Publisher
- Elsevier BV
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1016/j.isci.2026.115985,
title = {System-level FPGA validation of a trainable and robust multiplier-free spiking neural network},
author = {Qixuan Li and Lei Zhang},
year = {2026},
journal = {iScience},
doi = {10.1016/j.isci.2026.115985},
url = {https://doi.org/10.1016/j.isci.2026.115985}
}RIS
TY - JOUR TI - System-level FPGA validation of a trainable and robust multiplier-free spiking neural network AU - Qixuan Li AU - Lei Zhang PY - 2026 JO - iScience DO - 10.1016/j.isci.2026.115985 UR - https://doi.org/10.1016/j.isci.2026.115985 ER -
APA
Li, Q., & Zhang, L. (2026). System-level FPGA validation of a trainable and robust multiplier-free spiking neural network. iScience. https://doi.org/10.1016/j.isci.2026.115985
Source records
- crossref · retrieved 2026-09-25T22:46:26.376Z