Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
- DOI
- 10.1016/j.mee.2019.111005
- Published
- 2019-07
- Container
- Microelectronic Engineering
- Publisher
- Elsevier BV
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1016/j.mee.2019.111005,
title = {Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors},
author = {Renan Trevisoli and Rodrigo Trevisoli Doria and Sylvain Barraud and Marcelo Antonio Pavanello},
year = {2019},
journal = {Microelectronic Engineering},
doi = {10.1016/j.mee.2019.111005},
url = {https://doi.org/10.1016/j.mee.2019.111005}
}RIS
TY - JOUR TI - Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors AU - Renan Trevisoli AU - Rodrigo Trevisoli Doria AU - Sylvain Barraud AU - Marcelo Antonio Pavanello PY - 2019 JO - Microelectronic Engineering DO - 10.1016/j.mee.2019.111005 UR - https://doi.org/10.1016/j.mee.2019.111005 ER -
APA
Trevisoli, R., Doria, R. T., Barraud, S., & Pavanello, M. A. (2019). Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors. Microelectronic Engineering. https://doi.org/10.1016/j.mee.2019.111005
Source records
- crossref · retrieved 2026-11-10T09:40:58.869Z