Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications
- DOI
- 10.1016/j.mejo.2021.105034
- Published
- 2021-05
- Container
- Microelectronics Journal
- Publisher
- Elsevier BV
- Open access
- unknown
Credibility signals
uncertain Score 64/100 under policy 1.0.0. This is a metadata assessment, not a judgment of the paper's conclusions.
Show all credibility signals
- supportingDOI registered: A matching record was returned by Crossref.
- supportingDOI resolves: A matching record was returned by Crossref.
- not scoredDirectory of Open Access Journals: No matching DOAJ record was present in this response. No allow-list match; this is not evidence of low credibility.
- not scoredMEDLINE indexed: Not checked or no result supplied; no credibility inference made.
- not scoredOpenAlex core source: Not checked or no result supplied; no credibility inference made.
- not scoredKnown publisher allow-list: Not checked or no result supplied; no credibility inference made.
- not scoredROR affiliation: Not checked or no result supplied; no credibility inference made.
- not scoredRetraction Watch retraction: No retraction notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete.
- not scoredRetraction Watch expression of concern: No expression of concern notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete.
- not scoredRetraction Watch correction: No correction notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete.
- not scoredRetraction Watch reinstatement: No reinstatement notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete.
- not scoredOpen access status: Not checked or no result supplied; no credibility inference made.
- not scoredPublication license: Not checked or no result supplied; no credibility inference made.
- not scoredPublication version: A publication version was supplied but is not scored.
- supportingMetadata completeness: All 6 scored descriptive metadata groups are present.
Cite this work
BibTeX
@article{allodium:10.1016/j.mejo.2021.105034,
title = {Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications},
author = {Aibin Yan and Zhihui He and Jun Zhou and Jie Cui and Tianming Ni and Zhengfeng Huang and Xiaoqing Wen and Patrick Girard},
year = {2021},
journal = {Microelectronics Journal},
doi = {10.1016/j.mejo.2021.105034},
url = {https://doi.org/10.1016/j.mejo.2021.105034}
}RIS
TY - JOUR TI - Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications AU - Aibin Yan AU - Zhihui He AU - Jun Zhou AU - Jie Cui AU - Tianming Ni AU - Zhengfeng Huang AU - Xiaoqing Wen AU - Patrick Girard PY - 2021 JO - Microelectronics Journal DO - 10.1016/j.mejo.2021.105034 UR - https://doi.org/10.1016/j.mejo.2021.105034 ER -
APA
Yan, A., He, Z., Zhou, J., Cui, J., Ni, T., Huang, Z., Wen, X., & Girard, P. (2021). Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. Microelectronics Journal. https://doi.org/10.1016/j.mejo.2021.105034
Source records
- crossref · retrieved 2026-09-26T06:26:03.999Z