Gate mapping impact on variability robustness in FinFET technology
- DOI
- 10.1016/j.microrel.2019.113448
- Published
- 2019-09-23
- Container
- Microelectronics Reliability
- Publisher
- Not recorded
- Open access
- no
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Cite this work
BibTeX
@article{allodium:10.1016/j.microrel.2019.113448,
title = {Gate mapping impact on variability robustness in FinFET technology},
author = {Leonardo Heitich Brendler and Alexandra Lakmann Zimpeck and Cristina Meinhardt and Ricardo A.L. Reis},
year = {2019},
journal = {Microelectronics Reliability},
doi = {10.1016/j.microrel.2019.113448},
url = {https://doi.org/10.1016/j.microrel.2019.113448}
}RIS
TY - JOUR TI - Gate mapping impact on variability robustness in FinFET technology AU - Leonardo Heitich Brendler AU - Alexandra Lakmann Zimpeck AU - Cristina Meinhardt AU - Ricardo A.L. Reis PY - 2019 JO - Microelectronics Reliability DO - 10.1016/j.microrel.2019.113448 UR - https://doi.org/10.1016/j.microrel.2019.113448 ER -
APA
Brendler, L. H., Zimpeck, A. L., Meinhardt, C., & Reis, R. A. (2019). Gate mapping impact on variability robustness in FinFET technology. Microelectronics Reliability. https://doi.org/10.1016/j.microrel.2019.113448
Source records
- hal · retrieved 2026-09-26T17:41:07.699Z