Design and analysis of an efficient low power low delay low leakage clock keeper domino logic

Kurumaiah N, M. Kezia Joseph, P. Chandra Sekhar

Open source

DOI
10.1016/j.prime.2024.100525
Published
06
Container
e-Prime: Advances in Electrical Engineering, Electronics and Energy
Publisher
Not recorded
Open access
yes

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BibTeX

@article{allodium:10.1016/j.prime.2024.100525,
  title = {Design and analysis of an efficient low power low delay low leakage clock keeper domino logic},
  author = {Kurumaiah N and M. Kezia Joseph and P. Chandra Sekhar},
  year = {2024},
  journal = {e-Prime: Advances in Electrical Engineering, Electronics and Energy},
  doi = {10.1016/j.prime.2024.100525},
  url = {https://doi.org/10.1016/j.prime.2024.100525}
}

RIS

TY  - JOUR
TI  - Design and analysis of an efficient low power low delay low leakage clock keeper domino logic
AU  - Kurumaiah N
AU  - M. Kezia Joseph
AU  - P. Chandra Sekhar
PY  - 2024
JO  - e-Prime: Advances in Electrical Engineering, Electronics and Energy
DO  - 10.1016/j.prime.2024.100525
UR  - https://doi.org/10.1016/j.prime.2024.100525
ER  - 

APA

N, K., Joseph, M. K., & Sekhar, P. C. (2024). Design and analysis of an efficient low power low delay low leakage clock keeper domino logic. e-Prime: Advances in Electrical Engineering, Electronics and Energy. https://doi.org/10.1016/j.prime.2024.100525

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