A VLSI array architecture for Hough transform

K. Maharatna, Swapna Banerjee

Open source

DOI: 10.1016/s0031-3203(00)00080-7
Published: 2001-01
Container: Pattern Recognition
Publisher: Elsevier BV
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1016/s0031-3203-00-00080-7,
  title = {A VLSI array architecture for Hough transform},
  author = {K. Maharatna and Swapna Banerjee},
  year = {2001},
  journal = {Pattern Recognition},
  doi = {10.1016/s0031-3203(00)00080-7},
  url = {https://doi.org/10.1016/s0031-3203(00)00080-7}
}

RIS

TY  - JOUR
TI  - A VLSI array architecture for Hough transform
AU  - K. Maharatna
AU  - Swapna Banerjee
PY  - 2001
JO  - Pattern Recognition
DO  - 10.1016/s0031-3203(00)00080-7
UR  - https://doi.org/10.1016/s0031-3203(00)00080-7
ER  -

APA

Maharatna, K., & Banerjee, S. (2001). A VLSI array architecture for Hough transform. Pattern Recognition. https://doi.org/10.1016/s0031-3203(00)00080-7

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crossref · retrieved 2026-11-07T17:30:07.207Z