Gate-Dielectric Engineering with an Ultrathin Silicon Oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories.
- DOI
- 10.1021/acs.nanolett.5c05167
- Published
- 2026 Mar 18
- Container
- Nano letters
- Publisher
- Not recorded
- Open access
- no
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Cite this work
BibTeX
@article{allodium:10.1021/acs.nanolett.5c05167,
title = {Gate-Dielectric Engineering with an Ultrathin Silicon Oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories.},
author = {Athena FF and Hartanto J and Passlack M and Evans JC and Qin J and Dede D and Jana K and Liu S and Peña T and Pop E and Pitner G and Radu IP and McIntyre PC and Wong HP},
year = {2026},
journal = {Nano letters},
doi = {10.1021/acs.nanolett.5c05167},
url = {https://doi.org/10.1021/acs.nanolett.5c05167}
}RIS
TY - JOUR TI - Gate-Dielectric Engineering with an Ultrathin Silicon Oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories. AU - Athena FF AU - Hartanto J AU - Passlack M AU - Evans JC AU - Qin J AU - Dede D AU - Jana K AU - Liu S AU - Peña T AU - Pop E AU - Pitner G AU - Radu IP AU - McIntyre PC AU - Wong HP PY - 2026 JO - Nano letters DO - 10.1021/acs.nanolett.5c05167 UR - https://doi.org/10.1021/acs.nanolett.5c05167 ER -
APA
FF, A., J, H., M, P., JC, E., J, Q., D, D., K, J., S, L., T, P., E, P., G, P., IP, R., PC, M., & HP, W. (2026). Gate-Dielectric Engineering with an Ultrathin Silicon Oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories.. Nano letters. https://doi.org/10.1021/acs.nanolett.5c05167
Source records
- pubmed · retrieved 2026-09-27T16:07:54.446Z
- europe-pmc · retrieved 2026-09-27T16:07:54.462Z