Enhancement in Charge-Trapping Efficiency for InGaZnO Vertical-Channel Memory Transistors via Gate-Stack Engineering: Validation in the 40 nm Scaling Regime.
- DOI
- 10.1021/acsami.6c09875
- Published
- 2026 Sep 2
- Container
- ACS applied materials & interfaces
- Publisher
- Not recorded
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1021/acsami.6c09875,
title = {Enhancement in Charge-Trapping Efficiency for InGaZnO Vertical-Channel Memory Transistors via Gate-Stack Engineering: Validation in the 40 nm Scaling Regime.},
author = {Jung YJ and Hwang CS and Yoon SM},
year = {2026},
journal = {ACS applied materials \& interfaces},
doi = {10.1021/acsami.6c09875},
url = {https://doi.org/10.1021/acsami.6c09875}
}RIS
TY - JOUR TI - Enhancement in Charge-Trapping Efficiency for InGaZnO Vertical-Channel Memory Transistors via Gate-Stack Engineering: Validation in the 40 nm Scaling Regime. AU - Jung YJ AU - Hwang CS AU - Yoon SM PY - 2026 JO - ACS applied materials & interfaces DO - 10.1021/acsami.6c09875 UR - https://doi.org/10.1021/acsami.6c09875 ER -
APA
YJ, J., CS, H., & SM, Y. (2026). Enhancement in Charge-Trapping Efficiency for InGaZnO Vertical-Channel Memory Transistors via Gate-Stack Engineering: Validation in the 40 nm Scaling Regime.. ACS applied materials & interfaces. https://doi.org/10.1021/acsami.6c09875
Source records
- pubmed · retrieved 2026-11-10T09:45:48.735Z