A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors.
- DOI
- 10.1021/acsnano.5c04182
- Published
- 2025 Jul 15
- Container
- ACS nano
- Publisher
- Not recorded
- Open access
- yes
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Cite this work
BibTeX
@article{allodium:10.1021/acsnano.5c04182,
title = {A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors.},
author = {Zhao G and Wen W and Liao K and Coquet P and Wang X and Huang M and Tay BK},
year = {2025},
journal = {ACS nano},
doi = {10.1021/acsnano.5c04182},
url = {https://doi.org/10.1021/acsnano.5c04182}
}RIS
TY - JOUR TI - A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors. AU - Zhao G AU - Wen W AU - Liao K AU - Coquet P AU - Wang X AU - Huang M AU - Tay BK PY - 2025 JO - ACS nano DO - 10.1021/acsnano.5c04182 UR - https://doi.org/10.1021/acsnano.5c04182 ER -
APA
G, Z., W, W., K, L., P, C., X, W., M, H., & BK, T. (2025). A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors.. ACS nano. https://doi.org/10.1021/acsnano.5c04182
Source records
- pubmed · retrieved 2026-09-25T23:27:33.084Z
- europe-pmc · retrieved 2026-09-25T23:27:33.096Z