A Capacitively Coupled Dual-Gate 2D Transistor Unifying Logic-in-Memory and Tunable Synaptic Plasticity
- DOI
- 10.1021/acsnano.6c14423
- Published
- 2026-10-12
- Container
- ACS Nano
- Publisher
- American Chemical Society (ACS)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1021/acsnano.6c14423,
title = {A Capacitively Coupled
Dual-Gate 2D Transistor Unifying
Logic-in-Memory and Tunable Synaptic Plasticity},
author = {Min He and Gaochen Yang and Bo Jiang and Xiaohan Meng and Xiao He and Langlang Xu and Shengjie Lv and Guanting Liu and Xinyu Huang and Wenhao Shi and Weijia Lin and Mingjun Sun and Chunyu Liang and Jiaming Wu and Jiahao Huang and Lei Tong and Xiangshui Miao and Lei Ye},
year = {2026},
journal = {ACS Nano},
doi = {10.1021/acsnano.6c14423},
url = {https://doi.org/10.1021/acsnano.6c14423}
}RIS
TY - JOUR TI - A Capacitively Coupled Dual-Gate 2D Transistor Unifying Logic-in-Memory and Tunable Synaptic Plasticity AU - Min He AU - Gaochen Yang AU - Bo Jiang AU - Xiaohan Meng AU - Xiao He AU - Langlang Xu AU - Shengjie Lv AU - Guanting Liu AU - Xinyu Huang AU - Wenhao Shi AU - Weijia Lin AU - Mingjun Sun AU - Chunyu Liang AU - Jiaming Wu AU - Jiahao Huang AU - Lei Tong AU - Xiangshui Miao AU - Lei Ye PY - 2026 JO - ACS Nano DO - 10.1021/acsnano.6c14423 UR - https://doi.org/10.1021/acsnano.6c14423 ER -
APA
He, M., Yang, G., Jiang, B., Meng, X., He, X., Xu, L., Lv, S., Liu, G., Huang, X., Shi, W., Lin, W., Sun, M., Liang, C., Wu, J., Huang, J., Tong, L., Miao, X., & Ye, L. (2026). A Capacitively Coupled Dual-Gate 2D Transistor Unifying Logic-in-Memory and Tunable Synaptic Plasticity. ACS Nano. https://doi.org/10.1021/acsnano.6c14423
Source records
- crossref · retrieved 2026-11-08T06:24:01.417Z