A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

P. Girard, C. Landrault, V. Moreda, S. Pravossoudovitch, A. Virazel

Open source

DOI
10.1023/a:1008305507376
Published
1999-02
Container
Journal of Electronic Testing
Publisher
Springer Science and Business Media LLC
Open access
unknown

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BibTeX

@article{allodium:10.1023/a:1008305507376,
  title = {A Scan-BIST Structure to Test Delay Faults in Sequential Circuits},
  author = {P. Girard and C. Landrault and V. Moreda and S. Pravossoudovitch and A. Virazel},
  year = {1999},
  journal = {Journal of Electronic Testing},
  doi = {10.1023/a:1008305507376},
  url = {https://doi.org/10.1023/a:1008305507376}
}

RIS

TY  - JOUR
TI  - A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
AU  - P. Girard
AU  - C. Landrault
AU  - V. Moreda
AU  - S. Pravossoudovitch
AU  - A. Virazel
PY  - 1999
JO  - Journal of Electronic Testing
DO  - 10.1023/a:1008305507376
UR  - https://doi.org/10.1023/a:1008305507376
ER  - 

APA

Girard, P., Landrault, C., Moreda, V., Pravossoudovitch, S., & Virazel, A. (1999). A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. Journal of Electronic Testing. https://doi.org/10.1023/a:1008305507376

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