Dielectric stacking-engineered scalable reconfigurable transistor platform for adaptive logic circuits.
- DOI
- 10.1038/s41467-026-75864-2
- Published
- 2026 Jul 24
- Container
- Nature communications
- Publisher
- Not recorded
- Open access
- yes
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Cite this work
BibTeX
@article{allodium:10.1038/s41467-026-75864-2,
title = {Dielectric stacking-engineered scalable reconfigurable transistor platform for adaptive logic circuits.},
author = {Zhu P and Zhang C and Yang J and Guo YW and Huo S and Wu E and Wang F and Lin CY and Chen JH and Chu H and Liu Z and Zhao S and Li J and Li M and Lin YF and Zhang J},
year = {2026},
journal = {Nature communications},
doi = {10.1038/s41467-026-75864-2},
url = {https://doi.org/10.1038/s41467-026-75864-2}
}RIS
TY - JOUR TI - Dielectric stacking-engineered scalable reconfigurable transistor platform for adaptive logic circuits. AU - Zhu P AU - Zhang C AU - Yang J AU - Guo YW AU - Huo S AU - Wu E AU - Wang F AU - Lin CY AU - Chen JH AU - Chu H AU - Liu Z AU - Zhao S AU - Li J AU - Li M AU - Lin YF AU - Zhang J PY - 2026 JO - Nature communications DO - 10.1038/s41467-026-75864-2 UR - https://doi.org/10.1038/s41467-026-75864-2 ER -
APA
P, Z., C, Z., J, Y., YW, G., S, H., E, W., F, W., CY, L., JH, C., H, C., Z, L., S, Z., J, L., M, L., YF, L., & J, Z. (2026). Dielectric stacking-engineered scalable reconfigurable transistor platform for adaptive logic circuits.. Nature communications. https://doi.org/10.1038/s41467-026-75864-2
Source records
- pubmed · retrieved 2026-11-10T13:22:12.888Z