Efficient design and analysis of secure CMOS logic through logic encryption.

Chandra SS, Kannan RJ, Balaji BS, Veeramachaneni S, Noor Mahammad S

DOI: 10.1038/s41598-023-28007-2
Published: 2023 Jan 20
Container: Scientific reports
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.1038/s41598-023-28007-2,
  title = {Efficient design and analysis of secure CMOS logic through logic encryption.},
  author = {Chandra SS and Kannan RJ and Balaji BS and Veeramachaneni S and Noor Mahammad S},
  year = {2023},
  journal = {Scientific reports},
  doi = {10.1038/s41598-023-28007-2},
  url = {https://doi.org/10.1038/s41598-023-28007-2}
}

RIS

TY  - JOUR
TI  - Efficient design and analysis of secure CMOS logic through logic encryption.
AU  - Chandra SS
AU  - Kannan RJ
AU  - Balaji BS
AU  - Veeramachaneni S
AU  - Noor Mahammad S
PY  - 2023
JO  - Scientific reports
DO  - 10.1038/s41598-023-28007-2
UR  - https://doi.org/10.1038/s41598-023-28007-2
ER  -

APA

SS, C., RJ, K., BS, B., S, V., & S, N. M. (2023). Efficient design and analysis of secure CMOS logic through logic encryption.. Scientific reports. https://doi.org/10.1038/s41598-023-28007-2

Source records

pubmed · retrieved 2026-09-25T11:57:58.995Z