Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations
- DOI
- 10.1038/s41598-023-47890-3
- Published
- 2023-11-27
- Container
- Scientific Reports
- Publisher
- Springer Science and Business Media LLC
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1038/s41598-023-47890-3,
title = {Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations},
author = {Ankur Changela and Yogesh Kumar and Marcin Woźniak and Jana Shafi and Muhammad Fazal Ijaz},
year = {2023},
journal = {Scientific Reports},
doi = {10.1038/s41598-023-47890-3},
url = {https://doi.org/10.1038/s41598-023-47890-3}
}RIS
TY - JOUR TI - Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations AU - Ankur Changela AU - Yogesh Kumar AU - Marcin Woźniak AU - Jana Shafi AU - Muhammad Fazal Ijaz PY - 2023 JO - Scientific Reports DO - 10.1038/s41598-023-47890-3 UR - https://doi.org/10.1038/s41598-023-47890-3 ER -
APA
Changela, A., Kumar, Y., Woźniak, M., Shafi, J., & Ijaz, M. F. (2023). Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations. Scientific Reports. https://doi.org/10.1038/s41598-023-47890-3
Source records
- crossref · retrieved 2026-11-10T12:30:43.233Z