Low power and high-speed quadrate node upset tolerant latch design using CNTFET

Shaik Asiya, Satheesh Kumar S

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DOI: 10.1038/s41598-025-28311-z
Published: 2025-12-22
Container: Scientific Reports
Publisher: Springer Science and Business Media LLC
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1038/s41598-025-28311-z,
  title = {Low power and high-speed quadrate node upset tolerant latch design using CNTFET},
  author = {Shaik Asiya and Satheesh Kumar S},
  year = {2025},
  journal = {Scientific Reports},
  doi = {10.1038/s41598-025-28311-z},
  url = {https://doi.org/10.1038/s41598-025-28311-z}
}

RIS

TY  - JOUR
TI  - Low power and high-speed quadrate node upset tolerant latch design using CNTFET
AU  - Shaik Asiya
AU  - Satheesh Kumar S
PY  - 2025
JO  - Scientific Reports
DO  - 10.1038/s41598-025-28311-z
UR  - https://doi.org/10.1038/s41598-025-28311-z
ER  -

APA

Asiya, S., & S, S. K. (2025). Low power and high-speed quadrate node upset tolerant latch design using CNTFET. Scientific Reports. https://doi.org/10.1038/s41598-025-28311-z

Source records

crossref · retrieved 2026-11-10T16:36:41.395Z