Low power and high-speed quadrate node upset tolerant latch design using CNTFET.

Asiya S, S SK.

Open source

DOI: 10.1038/s41598-025-28311-z
Published: 2025-12-22
Container: Sci Rep
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.1038/s41598-025-28311-z,
  title = {Low power and high-speed quadrate node upset tolerant latch design using CNTFET.},
  author = {Asiya S and  S SK.},
  year = {2025},
  journal = {Sci Rep},
  doi = {10.1038/s41598-025-28311-z},
  url = {https://doi.org/10.1038/s41598-025-28311-z}
}

RIS

TY  - JOUR
TI  - Low power and high-speed quadrate node upset tolerant latch design using CNTFET.
AU  - Asiya S
AU  -  S SK.
PY  - 2025
JO  - Sci Rep
DO  - 10.1038/s41598-025-28311-z
UR  - https://doi.org/10.1038/s41598-025-28311-z
ER  -

APA

S, A., & SK., S. (2025). Low power and high-speed quadrate node upset tolerant latch design using CNTFET.. Sci Rep. https://doi.org/10.1038/s41598-025-28311-z

Source records

europe-pmc · retrieved 2026-09-26T04:05:53.289Z
doaj · retrieved 2026-09-26T04:05:53.280Z