Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfiguration
- DOI
- 10.1038/s41598-025-98473-3
- Published
- 2025-04-21
- Container
- Scientific Reports
- Publisher
- Springer Science and Business Media LLC
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1038/s41598-025-98473-3,
title = {Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfiguration},
author = {Sesibhushana Rao Bommana and Sreehari Veeramachaneni and Syed Ershad and MB Srinivas},
year = {2025},
journal = {Scientific Reports},
doi = {10.1038/s41598-025-98473-3},
url = {https://doi.org/10.1038/s41598-025-98473-3}
}RIS
TY - JOUR TI - Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfiguration AU - Sesibhushana Rao Bommana AU - Sreehari Veeramachaneni AU - Syed Ershad AU - MB Srinivas PY - 2025 JO - Scientific Reports DO - 10.1038/s41598-025-98473-3 UR - https://doi.org/10.1038/s41598-025-98473-3 ER -
APA
Bommana, S. R., Veeramachaneni, S., Ershad, S., & Srinivas, M. (2025). Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfiguration. Scientific Reports. https://doi.org/10.1038/s41598-025-98473-3
Source records
- crossref · retrieved 2026-09-25T16:51:07.134Z