Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field
- DOI
- 10.1038/s41598-025-99100-x
- Published
- 2025-04-29
- Container
- Scientific Reports
- Publisher
- Springer Science and Business Media LLC
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1038/s41598-025-99100-x,
title = {Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field},
author = {Md Rownak Hossain and Md Sazedur Rahman and Kh Shahriya Zaman and Walid El Fezzani and Mohammad Arif Sobhan Bhuiyan and Chia Chao Kang and Teh Jia Yew and Mahdi H. Miraz},
year = {2025},
journal = {Scientific Reports},
doi = {10.1038/s41598-025-99100-x},
url = {https://doi.org/10.1038/s41598-025-99100-x}
}RIS
TY - JOUR TI - Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field AU - Md Rownak Hossain AU - Md Sazedur Rahman AU - Kh Shahriya Zaman AU - Walid El Fezzani AU - Mohammad Arif Sobhan Bhuiyan AU - Chia Chao Kang AU - Teh Jia Yew AU - Mahdi H. Miraz PY - 2025 JO - Scientific Reports DO - 10.1038/s41598-025-99100-x UR - https://doi.org/10.1038/s41598-025-99100-x ER -
APA
Hossain, M. R., Rahman, M. S., Zaman, K. S., Fezzani, W. E., Bhuiyan, M. A. S., Kang, C. C., Yew, T. J., & Miraz, M. H. (2025). Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field. Scientific Reports. https://doi.org/10.1038/s41598-025-99100-x
Source records
- crossref · retrieved 2026-09-25T14:50:43.204Z