Efficient computation and design of high speed double precision Vedic multiplier architecture
- DOI
- 10.1038/s41598-026-38147-w
- Published
- 2026-02-05
- Container
- Scientific Reports
- Publisher
- Springer Science and Business Media LLC
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1038/s41598-026-38147-w,
title = {Efficient computation and design of high speed double precision Vedic multiplier architecture},
author = {Aruru Sai Kumar and G. Sahitya and Rambabu Kusuma and M. Sankush Krishna and B. Naresh Kumar Reddy and Suman Lata Tripathi},
year = {2026},
journal = {Scientific Reports},
doi = {10.1038/s41598-026-38147-w},
url = {https://doi.org/10.1038/s41598-026-38147-w}
}RIS
TY - JOUR TI - Efficient computation and design of high speed double precision Vedic multiplier architecture AU - Aruru Sai Kumar AU - G. Sahitya AU - Rambabu Kusuma AU - M. Sankush Krishna AU - B. Naresh Kumar Reddy AU - Suman Lata Tripathi PY - 2026 JO - Scientific Reports DO - 10.1038/s41598-026-38147-w UR - https://doi.org/10.1038/s41598-026-38147-w ER -
APA
Kumar, A. S., Sahitya, G., Kusuma, R., Krishna, M. S., Reddy, B. N. K., & Tripathi, S. L. (2026). Efficient computation and design of high speed double precision Vedic multiplier architecture. Scientific Reports. https://doi.org/10.1038/s41598-026-38147-w
Source records
- crossref · retrieved 2026-09-26T12:54:29.053Z