Power-efficient hardware architecture for 2-D multiple transforms in VVC.
- DOI
- 10.1038/s41598-026-40519-1
- Published
- 2026 Feb 19
- Container
- Scientific reports
- Publisher
- Not recorded
- Open access
- yes
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Cite this work
BibTeX
@article{allodium:10.1038/s41598-026-40519-1,
title = {Power-efficient hardware architecture for 2-D multiple transforms in VVC.},
author = {Palagani MB and Nalluri P},
year = {2026},
journal = {Scientific reports},
doi = {10.1038/s41598-026-40519-1},
url = {https://doi.org/10.1038/s41598-026-40519-1}
}RIS
TY - JOUR TI - Power-efficient hardware architecture for 2-D multiple transforms in VVC. AU - Palagani MB AU - Nalluri P PY - 2026 JO - Scientific reports DO - 10.1038/s41598-026-40519-1 UR - https://doi.org/10.1038/s41598-026-40519-1 ER -
APA
MB, P., & P, N. (2026). Power-efficient hardware architecture for 2-D multiple transforms in VVC.. Scientific reports. https://doi.org/10.1038/s41598-026-40519-1
Source records
- pubmed · retrieved 2026-11-10T14:02:13.785Z