SAT-inspired feature engineering with stacking ensemble learning for fault detection in digital logic circuits
- DOI
- 10.1038/s41598-026-50142-9
- Published
- 2026-05-04
- Container
- Scientific Reports
- Publisher
- Springer Science and Business Media LLC
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1038/s41598-026-50142-9,
title = {SAT-inspired feature engineering with stacking ensemble learning for fault detection in digital logic circuits},
author = {Sabareeswari Thangaganesan Chandradevi and Dhanagopal Ramachandran},
year = {2026},
journal = {Scientific Reports},
doi = {10.1038/s41598-026-50142-9},
url = {https://doi.org/10.1038/s41598-026-50142-9}
}RIS
TY - JOUR TI - SAT-inspired feature engineering with stacking ensemble learning for fault detection in digital logic circuits AU - Sabareeswari Thangaganesan Chandradevi AU - Dhanagopal Ramachandran PY - 2026 JO - Scientific Reports DO - 10.1038/s41598-026-50142-9 UR - https://doi.org/10.1038/s41598-026-50142-9 ER -
APA
Chandradevi, S. T., & Ramachandran, D. (2026). SAT-inspired feature engineering with stacking ensemble learning for fault detection in digital logic circuits. Scientific Reports. https://doi.org/10.1038/s41598-026-50142-9
Source records
- crossref · retrieved 2026-11-10T23:21:01.970Z