Dielectric and temperature-dependent optimization of an asymmetric gate–drain engineered core–shell dopingless nanotube tunnel FET for analog and RF performance
- DOI
- 10.1039/d6na00135a
- Published
- 2026
- Container
- Nanoscale Advances
- Publisher
- Royal Society of Chemistry (RSC)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1039/d6na00135a,
title = {Dielectric and temperature-dependent optimization of an asymmetric gate–drain engineered core–shell dopingless nanotube tunnel FET for analog and RF performance},
author = {Ranjith Kumar T. and Lakshmi Priya G.},
year = {2026},
journal = {Nanoscale Advances},
doi = {10.1039/d6na00135a},
url = {https://doi.org/10.1039/d6na00135a}
}RIS
TY - JOUR TI - Dielectric and temperature-dependent optimization of an asymmetric gate–drain engineered core–shell dopingless nanotube tunnel FET for analog and RF performance AU - Ranjith Kumar T. AU - Lakshmi Priya G. PY - 2026 JO - Nanoscale Advances DO - 10.1039/d6na00135a UR - https://doi.org/10.1039/d6na00135a ER -
APA
T., R. K., & G., L. P. (2026). Dielectric and temperature-dependent optimization of an asymmetric gate–drain engineered core–shell dopingless nanotube tunnel FET for analog and RF performance. Nanoscale Advances. https://doi.org/10.1039/d6na00135a
Source records
- crossref · retrieved 2026-09-25T00:12:09.855Z