Hardware realization of memory-augmented neural networks using multi-level RRAM arrays.

Kim G, Byun Y, Kim S, Kim S

DOI: 10.1039/d6nr02137a
Published: 2026 Sep 10
Container: Nanoscale
Publisher: Not recorded
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1039/d6nr02137a,
  title = {Hardware realization of memory-augmented neural networks using multi-level RRAM arrays.},
  author = {Kim G and Byun Y and Kim S and Kim S},
  year = {2026},
  journal = {Nanoscale},
  doi = {10.1039/d6nr02137a},
  url = {https://doi.org/10.1039/d6nr02137a}
}

RIS

TY  - JOUR
TI  - Hardware realization of memory-augmented neural networks using multi-level RRAM arrays.
AU  - Kim G
AU  - Byun Y
AU  - Kim S
AU  - Kim S
PY  - 2026
JO  - Nanoscale
DO  - 10.1039/d6nr02137a
UR  - https://doi.org/10.1039/d6nr02137a
ER  -

APA

G, K., Y, B., S, K., & S, K. (2026). Hardware realization of memory-augmented neural networks using multi-level RRAM arrays.. Nanoscale. https://doi.org/10.1039/d6nr02137a

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pubmed · retrieved 2026-09-25T20:17:30.969Z