Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level
- DOI
- 10.1049/iet-cds.2011.0352
- Published
- 2012-09-21
- Container
- IET Circuits, Devices & Systems
- Publisher
- Institution of Engineering and Technology (IET)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1049/iet-cds.2011.0352,
title = {Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level},
author = {O. Mbarek and A. Pegatoquet and M. Auguin},
year = {2012},
journal = {IET Circuits, Devices \& Systems},
doi = {10.1049/iet-cds.2011.0352},
url = {https://doi.org/10.1049/iet-cds.2011.0352}
}RIS
TY - JOUR TI - Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level AU - O. Mbarek AU - A. Pegatoquet AU - M. Auguin PY - 2012 JO - IET Circuits, Devices & Systems DO - 10.1049/iet-cds.2011.0352 UR - https://doi.org/10.1049/iet-cds.2011.0352 ER -
APA
Mbarek, O., Pegatoquet, A., & Auguin, M. (2012). Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level. IET Circuits, Devices & Systems. https://doi.org/10.1049/iet-cds.2011.0352
Source records
- crossref · retrieved 2026-11-06T11:29:22.528Z