Performance-driven macro-block placer for architectural evaluation of ASIC designs

V. Moshnyaga, Y. Mori, H. Onodera, K. Tamaru

Open source

DOI: 10.1049/ip-cds:19970643
Published: 1997
Container: IEE Proceedings - Circuits, Devices and Systems
Publisher: Institution of Engineering and Technology (IET)
Open access: unknown

Credibility signals

uncertain Score 64/100 under policy 1.0.0. This is a metadata assessment, not a judgment of the paper's conclusions.

Show all credibility signals

supportingDOI registered: A matching record was returned by Crossref. Source: Crossref; license: CC0 metadata
supportingDOI resolves: A matching record was returned by Crossref. Source: Crossref; license: CC0 metadata
not scoredDirectory of Open Access Journals: No matching DOAJ record was present in this response. No allow-list match; this is not evidence of low credibility. Source: DOAJ; license: CC0
not scoredMEDLINE indexed: Not checked or no result supplied; no credibility inference made. Source: No authority result supplied; license: Unknown
not scoredOpenAlex core source: Not checked or no result supplied; no credibility inference made. Source: No authority result supplied; license: Unknown
not scoredKnown publisher allow-list: Not checked or no result supplied; no credibility inference made. Source: No authority result supplied; license: Unknown
not scoredROR affiliation: Not checked or no result supplied; no credibility inference made. Source: No authority result supplied; license: Unknown
not scoredRetraction Watch retraction: No retraction notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete. Source: Retraction Watch; license: CC BY 4.0
not scoredRetraction Watch expression of concern: No expression of concern notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete. Source: Retraction Watch; license: CC BY 4.0
not scoredRetraction Watch correction: No correction notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete. Source: Retraction Watch; license: CC BY 4.0
not scoredRetraction Watch reinstatement: No reinstatement notice matched this DOI in the deployed snapshot. No matching event found; coverage may be incomplete. Source: Retraction Watch; license: CC BY 4.0
not scoredOpen access status: Not checked or no result supplied; no credibility inference made. Source: No authority result supplied; license: Unknown
not scoredPublication license: Not checked or no result supplied; no credibility inference made. Source: No authority result supplied; license: Unknown
not scoredPublication version: A publication version was supplied but is not scored. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer
supportingMetadata completeness: All 6 scored descriptive metadata groups are present. Source: Normalized work metadata; license: Caller-provided; provenance license not supplied to scorer

Cite this work

BibTeX

@article{allodium:10.1049/ip-cds:19970643,
  title = {Performance-driven macro-block placer for architectural evaluation of ASIC designs},
  author = {V. Moshnyaga and Y. Mori and H. Onodera and K. Tamaru},
  year = {1997},
  journal = {IEE Proceedings - Circuits, Devices and Systems},
  doi = {10.1049/ip-cds:19970643},
  url = {https://doi.org/10.1049/ip-cds:19970643}
}

RIS

TY  - JOUR
TI  - Performance-driven macro-block placer for architectural evaluation of ASIC designs
AU  - V. Moshnyaga
AU  - Y. Mori
AU  - H. Onodera
AU  - K. Tamaru
PY  - 1997
JO  - IEE Proceedings - Circuits, Devices and Systems
DO  - 10.1049/ip-cds:19970643
UR  - https://doi.org/10.1049/ip-cds:19970643
ER  -

APA

Moshnyaga, V., Mori, Y., Onodera, H., & Tamaru, K. (1997). Performance-driven macro-block placer for architectural evaluation of ASIC designs. IEE Proceedings - Circuits, Devices and Systems. https://doi.org/10.1049/ip-cds:19970643

Source records

crossref · retrieved 2026-09-27T17:18:38.538Z