Area efficient digital logic NOT gate using single electron box (SEB)

Bahrepour Davoud

Open source

DOI: 10.1051/smdo/2016017
Published: 2017
Container: International Journal for Simulation and Multidisciplinary Design Optimization
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.1051/smdo/2016017,
  title = {Area efficient digital logic NOT gate using single electron box (SEB)},
  author = {Bahrepour Davoud},
  year = {2017},
  journal = {International Journal for Simulation and Multidisciplinary Design Optimization},
  doi = {10.1051/smdo/2016017},
  url = {https://doi.org/10.1051/smdo/2016017}
}

RIS

TY  - JOUR
TI  - Area efficient digital logic NOT gate using single electron box (SEB)
AU  - Bahrepour Davoud
PY  - 2017
JO  - International Journal for Simulation and Multidisciplinary Design Optimization
DO  - 10.1051/smdo/2016017
UR  - https://doi.org/10.1051/smdo/2016017
ER  -

APA

Davoud, B. (2017). Area efficient digital logic NOT gate using single electron box (SEB). International Journal for Simulation and Multidisciplinary Design Optimization. https://doi.org/10.1051/smdo/2016017

Source records

doaj · retrieved 2026-09-25T09:21:07.627Z