A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade
- DOI
- 10.1088/1748-0221/11/02/c02063
- Published
- 2016
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- Not recorded
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- Open access
- no
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Cite this work
BibTeX
@article{allodium:10.1088/1748-0221/11/02/c02063,
title = {A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade},
author = {D. Magalotti and L. Alunni and N. Biesuz and G.M. Bilei and S. Citraro and F. Crescioli and L. Fanò and G. Fedi and G. Magazzù and L. Servoli and L. Storchi and F. Palla and P. Placidi and E. Rossi and A. Spiezia},
year = {2016},
doi = {10.1088/1748-0221/11/02/c02063},
url = {https://doi.org/10.1088/1748-0221/11/02/c02063}
}RIS
TY - JOUR TI - A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade AU - D. Magalotti AU - L. Alunni AU - N. Biesuz AU - G.M. Bilei AU - S. Citraro AU - F. Crescioli AU - L. Fanò AU - G. Fedi AU - G. Magazzù AU - L. Servoli AU - L. Storchi AU - F. Palla AU - P. Placidi AU - E. Rossi AU - A. Spiezia PY - 2016 DO - 10.1088/1748-0221/11/02/c02063 UR - https://doi.org/10.1088/1748-0221/11/02/c02063 ER -
APA
Magalotti, D., Alunni, L., Biesuz, N., Bilei, G., Citraro, S., Crescioli, F., Fanò, L., Fedi, G., Magazzù, G., Servoli, L., Storchi, L., Palla, F., Placidi, P., Rossi, E., & Spiezia, A. (2016). A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade. https://doi.org/10.1088/1748-0221/11/02/c02063
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- hal · retrieved 2026-11-10T14:15:48.931Z