High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector
- DOI
- 10.1088/1748-0221/14/12/c12012
- Published
- 2019
- Container
- Not recorded
- Publisher
- Not recorded
- Open access
- no
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Cite this work
BibTeX
@article{allodium:10.1088/1748-0221/14/12/c12012,
title = {High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector},
author = {X. Wei and W. Wei and T. Wu and Y. Zhang and X. Li and L. Zhang and W. Lu and Z. Liang and J. Dong and L. Li and J. Wang and R. Zheng and R. Casanova and S. Grinstein and Y. Hu and J.Guimaraes da Costa},
year = {2019},
doi = {10.1088/1748-0221/14/12/c12012},
url = {https://doi.org/10.1088/1748-0221/14/12/c12012}
}RIS
TY - JOUR TI - High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector AU - X. Wei AU - W. Wei AU - T. Wu AU - Y. Zhang AU - X. Li AU - L. Zhang AU - W. Lu AU - Z. Liang AU - J. Dong AU - L. Li AU - J. Wang AU - R. Zheng AU - R. Casanova AU - S. Grinstein AU - Y. Hu AU - J.Guimaraes da Costa PY - 2019 DO - 10.1088/1748-0221/14/12/c12012 UR - https://doi.org/10.1088/1748-0221/14/12/c12012 ER -
APA
Wei, X., Wei, W., Wu, T., Zhang, Y., Li, X., Zhang, L., Lu, W., Liang, Z., Dong, J., Li, L., Wang, J., Zheng, R., Casanova, R., Grinstein, S., Hu, Y., & Costa, J. D. (2019). High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector. https://doi.org/10.1088/1748-0221/14/12/c12012
Source records
- hal · retrieved 2026-09-26T00:23:05.480Z