Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC

A. Camplani, S. Dittmeier, A. Annovi, K. Axiotis, R. Beccherle, N. Biesuz, R. Brenner, S. Débieux, M. Ellert, P. Francavilla, P. Giannetti, K. Kordas, M. Mårtensson, P. Mastrandrea, C. Noulas, J. Oechsle, M. Piendibene, R. Poggi, A. Schöning, A. Sfyrla, C.L. Sotiropoulou, J. Steentoft, T. Tsiakiris, S. Xella, J. Zinßer

Open source

DOI: 10.1088/1748-0221/18/06/p06029
Published: 2023-06-01
Container: Journal of Instrumentation
Publisher: IOP Publishing
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1088/1748-0221/18/06/p06029,
  title = {Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC},
  author = {A. Camplani and S. Dittmeier and A. Annovi and K. Axiotis and R. Beccherle and N. Biesuz and R. Brenner and S. Débieux and M. Ellert and P. Francavilla and P. Giannetti and K. Kordas and M. Mårtensson and P. Mastrandrea and C. Noulas and J. Oechsle and M. Piendibene and R. Poggi and A. Schöning and A. Sfyrla and C.L. Sotiropoulou and J. Steentoft and T. Tsiakiris and S. Xella and J. Zinßer},
  year = {2023},
  journal = {Journal of Instrumentation},
  doi = {10.1088/1748-0221/18/06/p06029},
  url = {https://doi.org/10.1088/1748-0221/18/06/p06029}
}

RIS

TY  - JOUR
TI  - Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC
AU  - A. Camplani
AU  - S. Dittmeier
AU  - A. Annovi
AU  - K. Axiotis
AU  - R. Beccherle
AU  - N. Biesuz
AU  - R. Brenner
AU  - S. Débieux
AU  - M. Ellert
AU  - P. Francavilla
AU  - P. Giannetti
AU  - K. Kordas
AU  - M. Mårtensson
AU  - P. Mastrandrea
AU  - C. Noulas
AU  - J. Oechsle
AU  - M. Piendibene
AU  - R. Poggi
AU  - A. Schöning
AU  - A. Sfyrla
AU  - C.L. Sotiropoulou
AU  - J. Steentoft
AU  - T. Tsiakiris
AU  - S. Xella
AU  - J. Zinßer
PY  - 2023
JO  - Journal of Instrumentation
DO  - 10.1088/1748-0221/18/06/p06029
UR  - https://doi.org/10.1088/1748-0221/18/06/p06029
ER  -

APA

Camplani, A., Dittmeier, S., Annovi, A., Axiotis, K., Beccherle, R., Biesuz, N., Brenner, R., Débieux, S., Ellert, M., Francavilla, P., Giannetti, P., Kordas, K., Mårtensson, M., Mastrandrea, P., Noulas, C., Oechsle, J., Piendibene, M., Poggi, R., Schöning, A., Sfyrla, A., Sotiropoulou, C., Steentoft, J., Tsiakiris, T., Xella, S., & Zinßer, J. (2023). Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC. Journal of Instrumentation. https://doi.org/10.1088/1748-0221/18/06/p06029

Source records

crossref · retrieved 2026-09-27T11:27:56.154Z