A methodology for accurate benchmarking of neural network accelerators using a high-level synthesis-based hardware generator.

Prabhu K, Yu J, Pan XA, Raina P.

Open source

DOI
10.1098/rsta.2024.0514
Published
2026-02-01
Container
Philos Trans A Math Phys Eng Sci
Publisher
Not recorded
Open access
no

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BibTeX

@article{allodium:10.1098/rsta.2024.0514,
  title = {A methodology for accurate benchmarking of neural network accelerators using a high-level synthesis-based hardware generator.},
  author = {Prabhu K and  Yu J and  Pan XA and  Raina P.},
  year = {2026},
  journal = {Philos Trans A Math Phys Eng Sci},
  doi = {10.1098/rsta.2024.0514},
  url = {https://doi.org/10.1098/rsta.2024.0514}
}

RIS

TY  - JOUR
TI  - A methodology for accurate benchmarking of neural network accelerators using a high-level synthesis-based hardware generator.
AU  - Prabhu K
AU  -  Yu J
AU  -  Pan XA
AU  -  Raina P.
PY  - 2026
JO  - Philos Trans A Math Phys Eng Sci
DO  - 10.1098/rsta.2024.0514
UR  - https://doi.org/10.1098/rsta.2024.0514
ER  - 

APA

K, P., J, Y., XA, P., & P., R. (2026). A methodology for accurate benchmarking of neural network accelerators using a high-level synthesis-based hardware generator.. Philos Trans A Math Phys Eng Sci. https://doi.org/10.1098/rsta.2024.0514

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