Upset hardened memory design for submicron CMOS technology
- DOI
- 10.1109/23.556880
- Published
- 1996-12
- Container
- IEEE Transactions on Nuclear Science
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Open access
- unknown
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uncertain Score 64/100 under policy 1.0.0. This is a metadata assessment, not a judgment of the paper's conclusions.
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Cite this work
BibTeX
@article{allodium:10.1109/23.556880,
title = {Upset hardened memory design for submicron CMOS technology},
author = {T. Calin and M. Nicolaidis and R. Velazco},
year = {1996},
journal = {IEEE Transactions on Nuclear Science},
doi = {10.1109/23.556880},
url = {https://doi.org/10.1109/23.556880}
}RIS
TY - JOUR TI - Upset hardened memory design for submicron CMOS technology AU - T. Calin AU - M. Nicolaidis AU - R. Velazco PY - 1996 JO - IEEE Transactions on Nuclear Science DO - 10.1109/23.556880 UR - https://doi.org/10.1109/23.556880 ER -
APA
Calin, T., Nicolaidis, M., & Velazco, R. (1996). Upset hardened memory design for submicron CMOS technology. IEEE Transactions on Nuclear Science. https://doi.org/10.1109/23.556880
Source records
- crossref · retrieved 2026-11-06T19:11:32.536Z