An Enhanced Maximal Ratio Combiner for MIMO Systems With a Fast FPGA Implementation

Rafic Ayoubi, Jihad Daba, Samir Berjaoui, Moustapha El Hassan, Bachir Kabbara

Open source

DOI: 10.1109/access.2026.3684654
Published: 2026
Container: IEEE Access
Publisher: Not recorded
Open access: yes

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Cite this work

BibTeX

@article{allodium:10.1109/access.2026.3684654,
  title = {An Enhanced Maximal Ratio Combiner for MIMO Systems With a Fast FPGA Implementation},
  author = {Rafic Ayoubi and Jihad Daba and Samir Berjaoui and Moustapha El Hassan and Bachir Kabbara},
  year = {2026},
  journal = {IEEE Access},
  doi = {10.1109/access.2026.3684654},
  url = {https://doi.org/10.1109/access.2026.3684654}
}

RIS

TY  - JOUR
TI  - An Enhanced Maximal Ratio Combiner for MIMO Systems With a Fast FPGA Implementation
AU  - Rafic Ayoubi
AU  - Jihad Daba
AU  - Samir Berjaoui
AU  - Moustapha El Hassan
AU  - Bachir Kabbara
PY  - 2026
JO  - IEEE Access
DO  - 10.1109/access.2026.3684654
UR  - https://doi.org/10.1109/access.2026.3684654
ER  -

APA

Ayoubi, R., Daba, J., Berjaoui, S., Hassan, M. E., & Kabbara, B. (2026). An Enhanced Maximal Ratio Combiner for MIMO Systems With a Fast FPGA Implementation. IEEE Access. https://doi.org/10.1109/access.2026.3684654

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doaj · retrieved 2026-09-26T22:36:19.539Z