Fanout fault analysis for digital logic circuits
- DOI
- 10.1109/ats.1995.485313
- Published
- 1995
- Container
- Proceedings of the Fourth Asian Test Symposium
- Publisher
- IEEE
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/ats.1995.485313,
title = {Fanout fault analysis for digital logic circuits},
author = {J.E. Chen and Chung Len Lee and Wen Zen Shen and Beyin Chen},
year = {1995},
journal = {Proceedings of the Fourth Asian Test Symposium},
doi = {10.1109/ats.1995.485313},
url = {https://doi.org/10.1109/ats.1995.485313}
}RIS
TY - JOUR TI - Fanout fault analysis for digital logic circuits AU - J.E. Chen AU - Chung Len Lee AU - Wen Zen Shen AU - Beyin Chen PY - 1995 JO - Proceedings of the Fourth Asian Test Symposium DO - 10.1109/ats.1995.485313 UR - https://doi.org/10.1109/ats.1995.485313 ER -
APA
Chen, J., Lee, C. L., Shen, W. Z., & Chen, B. (1995). Fanout fault analysis for digital logic circuits. Proceedings of the Fourth Asian Test Symposium. https://doi.org/10.1109/ats.1995.485313
Source records
- crossref · retrieved 2026-09-27T07:47:08.598Z