An on-chip low power clock multiplier unit in 0.25 micron technology
- DOI
- 10.1109/ccece.2005.1557318
- Published
- Not recorded
- Container
- Canadian Conference on Electrical and Computer Engineering, 2005.
- Publisher
- IEEE
- Open access
- unknown
Credibility signals
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Cite this work
BibTeX
@article{allodium:10.1109/ccece.2005.1557318,
title = {An on-chip low power clock multiplier unit in 0.25 micron technology},
author = {M.T. Hossain Setu and G.R. Krishnam Raju and R. Weerasekera},
journal = {Canadian Conference on Electrical and Computer Engineering, 2005.},
doi = {10.1109/ccece.2005.1557318},
url = {https://doi.org/10.1109/ccece.2005.1557318}
}RIS
TY - JOUR TI - An on-chip low power clock multiplier unit in 0.25 micron technology AU - M.T. Hossain Setu AU - G.R. Krishnam Raju AU - R. Weerasekera JO - Canadian Conference on Electrical and Computer Engineering, 2005. DO - 10.1109/ccece.2005.1557318 UR - https://doi.org/10.1109/ccece.2005.1557318 ER -
APA
Setu, M. H., Raju, G. K., & Weerasekera, R. (n.d.). An on-chip low power clock multiplier unit in 0.25 micron technology. Canadian Conference on Electrical and Computer Engineering, 2005.. https://doi.org/10.1109/ccece.2005.1557318
Source records
- crossref · retrieved 2026-09-25T17:53:18.083Z