Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher
- DOI
- 10.1109/dsd.2016.46
- Published
- 2016-08
- Container
- 2016 Euromicro Conference on Digital System Design (DSD)
- Publisher
- IEEE
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/dsd.2016.46,
title = {Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher},
author = {Carlos Andres Lara-Nino and Miguel Morales-Sandoval and Arturo Diaz-Perez},
year = {2016},
journal = {2016 Euromicro Conference on Digital System Design (DSD)},
doi = {10.1109/dsd.2016.46},
url = {https://doi.org/10.1109/dsd.2016.46}
}RIS
TY - JOUR TI - Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher AU - Carlos Andres Lara-Nino AU - Miguel Morales-Sandoval AU - Arturo Diaz-Perez PY - 2016 JO - 2016 Euromicro Conference on Digital System Design (DSD) DO - 10.1109/dsd.2016.46 UR - https://doi.org/10.1109/dsd.2016.46 ER -
APA
Lara-Nino, C. A., Morales-Sandoval, M., & Diaz-Perez, A. (2016). Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher. 2016 Euromicro Conference on Digital System Design (DSD). https://doi.org/10.1109/dsd.2016.46
Source records
- crossref · retrieved 2026-11-08T20:30:22.566Z