DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks
- DOI
- 10.1109/fpl57034.2022.00035
- Published
- 2022-08
- Container
- 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)
- Publisher
- IEEE
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/fpl57034.2022.00035,
title = {DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks},
author = {Jan Sommer and M. Akif Ozkan and Oliver Keszocze and Jurgen Teich},
year = {2022},
journal = {2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)},
doi = {10.1109/fpl57034.2022.00035},
url = {https://doi.org/10.1109/fpl57034.2022.00035}
}RIS
TY - JOUR TI - DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks AU - Jan Sommer AU - M. Akif Ozkan AU - Oliver Keszocze AU - Jurgen Teich PY - 2022 JO - 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL) DO - 10.1109/fpl57034.2022.00035 UR - https://doi.org/10.1109/fpl57034.2022.00035 ER -
APA
Sommer, J., Ozkan, M. A., Keszocze, O., & Teich, J. (2022). DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL). https://doi.org/10.1109/fpl57034.2022.00035
Source records
- crossref · retrieved 2026-09-25T14:37:50.901Z