A high speed low power adder in dynamic logic base on transmission gate
- DOI
- 10.1109/iccpct.2015.7159408
- Published
- 2015-03
- Container
- 2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]
- Publisher
- IEEE
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/iccpct.2015.7159408,
title = {A high speed low power adder in dynamic logic base on transmission gate},
author = {Neeraj Jain and Puran Gour and Brahmi Shrman},
year = {2015},
journal = {2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]},
doi = {10.1109/iccpct.2015.7159408},
url = {https://doi.org/10.1109/iccpct.2015.7159408}
}RIS
TY - JOUR TI - A high speed low power adder in dynamic logic base on transmission gate AU - Neeraj Jain AU - Puran Gour AU - Brahmi Shrman PY - 2015 JO - 2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015] DO - 10.1109/iccpct.2015.7159408 UR - https://doi.org/10.1109/iccpct.2015.7159408 ER -
APA
Jain, N., Gour, P., & Shrman, B. (2015). A high speed low power adder in dynamic logic base on transmission gate. 2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]. https://doi.org/10.1109/iccpct.2015.7159408
Source records
- crossref · retrieved 2026-09-25T06:44:03.572Z