Securing embedded programmable gate arrays in secure circuits

N. Valette, L. Torres, G. Sassatelli, F. Bancel

Open source

DOI
10.1109/ipdps.2006.1639483
Published
2006
Container
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
Publisher
IEEE
Open access
unknown

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BibTeX

@article{allodium:10.1109/ipdps.2006.1639483,
  title = {Securing embedded programmable gate arrays in secure circuits},
  author = {N. Valette and L. Torres and G. Sassatelli and F. Bancel},
  year = {2006},
  journal = {Proceedings 20th IEEE International Parallel \& Distributed Processing Symposium},
  doi = {10.1109/ipdps.2006.1639483},
  url = {https://doi.org/10.1109/ipdps.2006.1639483}
}

RIS

TY  - JOUR
TI  - Securing embedded programmable gate arrays in secure circuits
AU  - N. Valette
AU  - L. Torres
AU  - G. Sassatelli
AU  - F. Bancel
PY  - 2006
JO  - Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
DO  - 10.1109/ipdps.2006.1639483
UR  - https://doi.org/10.1109/ipdps.2006.1639483
ER  - 

APA

Valette, N., Torres, L., Sassatelli, G., & Bancel, F. (2006). Securing embedded programmable gate arrays in secure circuits. Proceedings 20th IEEE International Parallel & Distributed Processing Symposium. https://doi.org/10.1109/ipdps.2006.1639483

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