Partitioning constraints and signal routing approach for multi-FPGA prototyping platform

Mariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid

DOI: 10.1109/issoc.2013.6675273
Published: 2013
Container: Not recorded
Publisher: IEEE
Open access: no

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Cite this work

BibTeX

@article{allodium:10.1109/issoc.2013.6675273,
  title = {Partitioning constraints and signal routing approach for multi-FPGA prototyping platform},
  author = {Mariem Turki and Habib Mehrez and Zied Marrakchi and Mohamed Abid},
  year = {2013},
  doi = {10.1109/issoc.2013.6675273},
  url = {https://doi.org/10.1109/issoc.2013.6675273}
}

RIS

TY  - JOUR
TI  - Partitioning constraints and signal routing approach for multi-FPGA prototyping platform
AU  - Mariem Turki
AU  - Habib Mehrez
AU  - Zied Marrakchi
AU  - Mohamed Abid
PY  - 2013
DO  - 10.1109/issoc.2013.6675273
UR  - https://doi.org/10.1109/issoc.2013.6675273
ER  -

APA

Turki, M., Mehrez, H., Marrakchi, Z., & Abid, M. (2013). Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. https://doi.org/10.1109/issoc.2013.6675273

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hal · retrieved 2026-09-25T13:44:18.087Z