Systemc model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementation

C. Tanougast, Y. Berviller, C. Mannino, Hassan Rabah, M. Janiaut, Serge Weber

DOI: 10.1109/iwrsp.2004.1311111
Published: 2013-06-24
Container: Not recorded
Publisher: IEEE
Open access: no

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Cite this work

BibTeX

@article{allodium:10.1109/iwrsp.2004.1311111,
  title = {Systemc model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementation},
  author = {C. Tanougast and Y. Berviller and C. Mannino and Hassan Rabah and M. Janiaut and Serge Weber},
  year = {2013},
  doi = {10.1109/iwrsp.2004.1311111},
  url = {https://doi.org/10.1109/iwrsp.2004.1311111}
}

RIS

TY  - JOUR
TI  - Systemc model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementation
AU  - C. Tanougast
AU  - Y. Berviller
AU  - C. Mannino
AU  - Hassan Rabah
AU  - M. Janiaut
AU  - Serge Weber
PY  - 2013
DO  - 10.1109/iwrsp.2004.1311111
UR  - https://doi.org/10.1109/iwrsp.2004.1311111
ER  -

APA

Tanougast, C., Berviller, Y., Mannino, C., Rabah, H., Janiaut, M., & Weber, S. (2013). Systemc model of a MPEG-2 DVB-T bit-rate measurement architecture for FPGA implementation. https://doi.org/10.1109/iwrsp.2004.1311111

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hal · retrieved 2026-09-25T19:04:46.505Z