A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing
- DOI
- 10.1109/jssc.2018.2886325
- Published
- 2019
- Container
- IEEE Journal of Solid-State Circuits
- Publisher
- Not recorded
- Open access
- no
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Cite this work
BibTeX
@article{allodium:10.1109/jssc.2018.2886325,
title = {A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing},
author = {Laurent Millet and Stéphane Chevobbe and Caaliph Andriamisaina and Lamine Benaissa and Edouard Deschaseaux and Edith Beigné and Karim Ben Chehida and Maria Lepecq and Mehdi Darouich and Fabrice Guellec and Dombek Thomas and Marc Duranton},
year = {2019},
journal = {IEEE Journal of Solid-State Circuits},
doi = {10.1109/jssc.2018.2886325},
url = {https://doi.org/10.1109/jssc.2018.2886325}
}RIS
TY - JOUR TI - A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing AU - Laurent Millet AU - Stéphane Chevobbe AU - Caaliph Andriamisaina AU - Lamine Benaissa AU - Edouard Deschaseaux AU - Edith Beigné AU - Karim Ben Chehida AU - Maria Lepecq AU - Mehdi Darouich AU - Fabrice Guellec AU - Dombek Thomas AU - Marc Duranton PY - 2019 JO - IEEE Journal of Solid-State Circuits DO - 10.1109/jssc.2018.2886325 UR - https://doi.org/10.1109/jssc.2018.2886325 ER -
APA
Millet, L., Chevobbe, S., Andriamisaina, C., Benaissa, L., Deschaseaux, E., Beigné, E., Chehida, K. B., Lepecq, M., Darouich, M., Guellec, F., Thomas, D., & Duranton, M. (2019). A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/jssc.2018.2886325
Source records
- hal · retrieved 2026-11-10T10:16:59.102Z