A 30% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants
- DOI
- 10.1109/jssc.2022.3180633
- Published
- 2022-11
- Container
- IEEE Journal of Solid-State Circuits
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/jssc.2022.3180633,
title = {A 30\% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants},
author = {Ziyue Xu and Adam Khalifa and Ankit Mittal and Mehdi Nasrollahpourmotlaghzanjani and Diptashree Das and Marvin Onabajo and Nian Xiang Sun and Sydney S. Cash and Aatmesh Shrivastava},
year = {2022},
journal = {IEEE Journal of Solid-State Circuits},
doi = {10.1109/jssc.2022.3180633},
url = {https://doi.org/10.1109/jssc.2022.3180633}
}RIS
TY - JOUR TI - A 30% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants AU - Ziyue Xu AU - Adam Khalifa AU - Ankit Mittal AU - Mehdi Nasrollahpourmotlaghzanjani AU - Diptashree Das AU - Marvin Onabajo AU - Nian Xiang Sun AU - Sydney S. Cash AU - Aatmesh Shrivastava PY - 2022 JO - IEEE Journal of Solid-State Circuits DO - 10.1109/jssc.2022.3180633 UR - https://doi.org/10.1109/jssc.2022.3180633 ER -
APA
Xu, Z., Khalifa, A., Mittal, A., Nasrollahpourmotlaghzanjani, M., Das, D., Onabajo, M., Sun, N. X., Cash, S. S., & Shrivastava, A. (2022). A 30% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/jssc.2022.3180633
Source records
- crossref · retrieved 2026-09-25T11:52:49.638Z