Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors

Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu

Open source

DOI: 10.1109/mdt.2007.202
Published: 2007-11
Container: IEEE Design & Test of Computers
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Open access: unknown

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Cite this work

BibTeX

@article{allodium:10.1109/mdt.2007.202,
  title = {Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors},
  author = {Sylvain Guilley and Florent Flament and Philippe Hoogvorst and Renaud Pacalet and Yves Mathieu},
  year = {2007},
  journal = {IEEE Design \&amp; Test of Computers},
  doi = {10.1109/mdt.2007.202},
  url = {https://doi.org/10.1109/mdt.2007.202}
}

RIS

TY  - JOUR
TI  - Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
AU  - Sylvain Guilley
AU  - Florent Flament
AU  - Philippe Hoogvorst
AU  - Renaud Pacalet
AU  - Yves Mathieu
PY  - 2007
JO  - IEEE Design &amp; Test of Computers
DO  - 10.1109/mdt.2007.202
UR  - https://doi.org/10.1109/mdt.2007.202
ER  -

APA

Guilley, S., Flament, F., Hoogvorst, P., Pacalet, R., & Mathieu, Y. (2007). Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Design & Test of Computers. https://doi.org/10.1109/mdt.2007.202

Source records

crossref · retrieved 2026-11-10T10:14:03.666Z