Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)
- DOI
- 10.1109/mtv.2003.1250257
- Published
- Not recorded
- Container
- Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions
- Publisher
- IEEE
- Open access
- unknown
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Cite this work
BibTeX
@article{allodium:10.1109/mtv.2003.1250257,
title = {Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)},
author = {F. Hunsinger and S. Francois and A.A. Jerraya},
journal = {Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions},
doi = {10.1109/mtv.2003.1250257},
url = {https://doi.org/10.1109/mtv.2003.1250257}
}RIS
TY - JOUR TI - Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC) AU - F. Hunsinger AU - S. Francois AU - A.A. Jerraya JO - Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions DO - 10.1109/mtv.2003.1250257 UR - https://doi.org/10.1109/mtv.2003.1250257 ER -
APA
Hunsinger, F., Francois, S., & Jerraya, A. (n.d.). Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC). Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions. https://doi.org/10.1109/mtv.2003.1250257
Source records
- crossref · retrieved 2026-09-25T10:04:54.643Z